mini_jit::instructions

mini_jit::instructions::base

constexpr uint32_t mini_jit::instructions::base::add(gpr_t reg_dest, gpr_t reg_src, uint32_t imm12, uint32_t shift)

Generates an ADD (immediate) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – source register.
imm12 – 12-bit immediate value.
shift – shift value.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::add(gpr_t reg_dest, gpr_t reg_src1, gpr_t reg_src2, uint32_t imm6, uint32_t shift)

Generates an ADD (shifted register) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
imm6 – 6-bit immediate value.
shift – shift value.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::cbnz(gpr_t reg, int32_t imm19)

Generates a CBNZ instruction.

Parameters:

reg – general-purpose register.
imm19 – immediate value (not the offset bytes!).

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::ldp(gpr_t reg_dest1, gpr_t reg_dest2, gpr_t reg_src, int32_t imm7)

Generates a base LDP instruction using signed offset encoding.

Parameters:

reg_dest1 – first destination register.
reg_dest2 – second destination register.
reg_src – source register (base address).
imm7 – 7-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::ldpPost(gpr_t reg_dest1, gpr_t reg_dest2, gpr_t reg_src, int32_t imm7)

Generates a base LDP instruction using post-index encoding.

Parameters:

reg_dest1 – first destination register.
reg_dest2 – second destination register.
reg_src – source register (base address).
imm7 – 7-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::ldpPre(gpr_t reg_dest1, gpr_t reg_dest2, gpr_t reg_src, int32_t imm7)

Generates a base LDP instruction using pre-index encoding.

Parameters:

reg_dest1 – first destination register.
reg_dest2 – second destination register.
reg_src – source register (base address).
imm7 – 7-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::ldr(gpr_t reg_dest, gpr_t reg_src, uint32_t imm)

Generates a base LDR (12-bit immediate) instruction using unsigned offset encoding.

Parameters:

reg_dest – destination register.
reg_src – source register (base address).
imm12 – 12-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::lsl(gpr_t reg_dest, gpr_t reg_src, uint32_t imm)

Generates a base LSL (immediate) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
imm12 – immediate value.

constexpr uint32_t mini_jit::instructions::base::mov(gpr_t reg_dest, gpr_t reg_src)

Generates an MOV (register) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::mov(gpr_t reg_dest, uint64_t imm16)

Generates an MOV 16-bit immediate instruction.

Parameters:

reg_dest – destination register.
imm16 – 16-bit unsigned immediate value.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::movSP(gpr_t reg_dest, gpr_t reg_src)

Generates an MOV (from/to SP) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – source register.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::movk(gpr_t reg_dest, uint16_t imm16, uint32_t shift)

Generates an MOVK instruction.

Parameters:

reg_dest – destination register.
imm16 – 16-bit unsigned immediate value.
shift – amount by which to left shift the immediate value.

constexpr uint32_t mini_jit::instructions::base::movz(gpr_t reg_dest, uint16_t imm16, uint32_t shift)

Generates an MOVZ instruction.

Parameters:

reg_dest – destination register.
imm16 – 16-bit unsigned immediate value.
shift – amount by which to left shift the immediate value.

constexpr uint32_t mini_jit::instructions::base::mul(gpr_t reg_dest, gpr_t reg_src1, gpr_t reg_src2)

Generates an MUL (register) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::orr(gpr_t reg_dest, gpr_t reg_src1, gpr_t reg_src2, uint32_t shift, uint32_t amount)

Generates an ORR (shifted register) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
shift – shift value.
amount – amount to shift.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::base::ret()

Generates a RET instruction.

Returns:: instruction.

constexpr uint32_t mini_jit::instructions::base::stp(gpr_t reg_data1, gpr_t reg_data2, gpr_t reg_address, int32_t imm7)

Generates an STP instruction using signed offset encoding.

Parameters:

reg_data1 – first register holding the data to be transferred.
reg_data2 – second register holding the data to be transferred.
reg_address – register holding the memory address.
imm7 – 7-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::stpPost(gpr_t reg_data1, gpr_t reg_data2, gpr_t reg_address, int32_t imm7)

Generates an STP instruction using post-index encoding.

Parameters:

reg_data1 – first register holding the data to be transferred.
reg_data2 – second register holding the data to be transferred.
reg_address – register holding the memory address.
imm7 – 7-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::stpPre(gpr_t reg_data1, gpr_t reg_data2, gpr_t reg_address, int32_t imm7)

Generates an STP instruction using pre-index encoding.

Parameters:

reg_data1 – first register holding the data to be transferred.
reg_data2 – second register holding the data to be transferred.
reg_address – register holding the memory address.
imm7 – 7-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::str(gpr_t reg_data, gpr_t reg_address, uint32_t imm12)

Generates an STR (12-bit immediate) instruction using unsigned offset encoding.

Parameters:

reg_data – register holding the data to be transferred.
reg_address – register holding the memory address.
imm12 – 12-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::strPost(gpr_t reg_data, gpr_t reg_address, uint32_t imm9)

Generates an STR (9-bit immediate) instruction using post-index encoding.

Parameters:

reg_data – register holding the data to be transferred.
reg_address – register holding the memory address.
imm9 – signed 9-bit immediate value.

constexpr uint32_t mini_jit::instructions::base::sub(gpr_t reg_dest, gpr_t reg_src, uint32_t imm12, uint32_t shift)

Generates an SUB (immediate) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
imm12 – 12-bit immediate value.
shift – shift value.

Returns:

instruction.

mini_jit::instructions::simd_fp

constexpr uint32_t mini_jit::instructions::simd_fp::eor(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an EOR (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier (8B or 16B).

constexpr uint32_t mini_jit::instructions::simd_fp::fabsVec(simd_fp_t reg_dest, simd_fp_t reg_src, arr_spec_t arr_spec)

Generates an FABS (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
arr_spec – arrangement specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::fabsScalar(simd_fp_t reg_dest, simd_fp_t reg_src, neon_size_spec_t size_spec)

Generates an FABS (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
size_spec – size specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::faddVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FADD (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::faddScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec)

Generates an FADD (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fcmp(simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec, bool zero)

Generates an FCMP (scalar) instruction.

Parameters:

reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier.
zero – specifies the opcode.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fcvtmsVec(simd_fp_t reg_dest, simd_fp_t reg_src1, arr_spec_t arr_spec)

Generates an FCVTMS (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fcvtmsScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, neon_size_spec_t size_spec)

Generates an FCVTMS (scalar SIMD&FP) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fdivVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FDIV (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fdivScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec)

Generates an FDIV (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmadd(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, simd_fp_t reg_src3, neon_size_spec_t size_spec)

Generates an FMADD instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register (multiplicand).
reg_src2 – second source register (multiplier).
reg_src3 – third source register (addend).
size_spec – size specifier (s or d).

constexpr uint32_t mini_jit::instructions::simd_fp::fmaxScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec)

Generates an FMAX (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier (s or d).

constexpr uint32_t mini_jit::instructions::simd_fp::fmaxVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FMAX (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec_t – arrangement specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::fminScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec)

Generates an FMIN (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier (s or d).

constexpr uint32_t mini_jit::instructions::simd_fp::fminVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FMIN (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec_t – arrangement specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::fmlaVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FMLA (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmlaElem(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FMLA (by element) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmovVec(simd_fp_t reg_dest, int32_t imm8, arr_spec_t arr_spec)

Generates an FMOV (vector, immediate) instruction.

Parameters:

reg_dest – destination register.
imm8 – 8-bit immediate (sign bit, 3-bit exponent, 4-bit precision).
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmovScalar(simd_fp_t reg_dest, int32_t imm8, neon_size_spec_t size_spec)

Generates an FMOV (scalar, immediate) instruction.

Parameters:

reg_dest – destination register.
imm8 – 8-bit immediate (sign bit, 3-bit exponent, 4-bit precision).
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmovIntVec(simd_fp_t reg_dest, int32_t imm8, arr_spec_t arr_spec)

Generates an FMOV (vector, immediate) instruction.

Parameters:

reg_dest – destination register.
imm8 – 8-bit integer value to move.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmovIntScalar(simd_fp_t reg_dest, int32_t imm8, neon_size_spec_t size_spec)

Generates an FMOV (scalar, immediate) instruction.

Parameters:

reg_dest – destination register.
imm8 – 8-bit integer value to move.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmulVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FMUL (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fmulScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec)

Generates an FMUL (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::frecpeVec(simd_fp_t reg_dest, simd_fp_t reg_src, arr_spec_t arr_spec)

Generates a vector FRECPE (Floating-point reciprocal estimate) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
arr_spec – arrangement specifier (2s, 4s or 2d).

constexpr uint32_t mini_jit::instructions::simd_fp::frecpeScalar(simd_fp_t reg_dest, simd_fp_t reg_src, size_spec_t size_spec)

Generates a scalar FRECPE (Floating-point reciprocal estimate) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
size_spec – size specifier (s, d).

constexpr uint32_t mini_jit::instructions::simd_fp::frecpsVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates a vector FRECPS (Floating-point reciprocal step) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier (2s, 4s or 2d).

constexpr uint32_t mini_jit::instructions::simd_fp::frecpsScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, size_spec_t size_spec)

Generates a scalar FRECPS (Floating-point reciprocal step) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier (s, d).

constexpr uint32_t mini_jit::instructions::simd_fp::frintmVec(simd_fp_t reg_dest, simd_fp_t reg_src, arr_spec_t arr_spec)

Generates an FRINTM (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::frintmScalar(simd_fp_t reg_dest, simd_fp_t reg_src, neon_size_spec_t size_spec)

Generates an FRINTM (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::frintnVec(simd_fp_t reg_dest, simd_fp_t reg_src, arr_spec_t arr_spec)

Generates an FRINTN (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::frintnScalar(simd_fp_t reg_dest, simd_fp_t reg_src, neon_size_spec_t size_spec)

Generates an FRINTN (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fsubVec(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an FSUB (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::fsubScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, neon_size_spec_t size_spec)

Generates an FSUB (scalar) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::ins(simd_fp_t reg_dest, simd_fp_t reg_src, uint32_t imm5, uint32_t imm4, neon_size_spec_t size_spec)

Generates an INS (element) instruction.

Parameters:

reg_dest – destination register.
reg_src2 – source register.
imm5 – 5-bit immediate (destination index).
imm4 – 4-bit immediate (source index).

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::ld1(simd_fp_t reg_dst, gpr_t reg_src, uint32_t index, neon_size_spec_t size)

Generates an LD1 instruction (single structure) with a lane index, e.g. LD1 {V0.S}[0], [X0].

!

Parameters:

reg_dst – Destination SIMD register.
reg_src – Source general-purpose register containing the address.
index – Index of the lane to load to.
size – Size of the SIMD register (s or d).

constexpr uint32_t mini_jit::instructions::simd_fp::ld1(simd_fp_t reg_dst, gpr_t reg_src, uint32_t index, neon_size_spec_t size, gpr_t reg_post_index)

Generates an LD1 instruction (single structure) with a lane index and a register post-index, e.g. LD1 {V0.S}[0], [X0], X1.

!

Parameters:

reg_dst – Destination SIMD register.
reg_src – Source general-purpose register containing the address.
index – Index of the lane to load to.
size – Size of the SIMD register (s or d).
post_index – Post-index register to add to the address in reg_src.

constexpr uint32_t mini_jit::instructions::simd_fp::ld1(simd_fp_t reg_dst, gpr_t reg_src, uint32_t index, neon_size_spec_t size, uint32_t post_index)

Generates an LD1 instruction (single structure) with a lane index and a post-index immediate, e.g. LD1 {V0.S}[0], [X0], #4.

!

Parameters:

reg_dst – Destination SIMD register.
reg_src – Source general-purpose register containing the address.
index – Index of the lane to load to.
size – Size of the SIMD register (s or d).
post_index – Post-index immediate to add to the address in reg_src.

constexpr uint32_t mini_jit::instructions::simd_fp::ldp(simd_fp_t reg_dest1, simd_fp_t reg_dest2, gpr_t reg_src, int32_t imm7, neon_size_spec_t size_spec)

Generates an LDP instruction using signed offset encoding.

Parameters:

reg_dest1 – first destination register.
reg_dest2 – second destination register.
reg_src – source register (base address).
imm7 – 7-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::ldpPost(simd_fp_t reg_dest1, simd_fp_t reg_dest2, gpr_t reg_src, int32_t imm7, neon_size_spec_t size_spec)

Generates an LDP instruction using post-index encoding.

Parameters:

reg_dest1 – first destination register.
reg_dest2 – second destination register.
reg_src – source register (base address).
imm7 – 7-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::ldpPre(simd_fp_t reg_dest1, simd_fp_t reg_dest2, gpr_t reg_src, int32_t imm7, neon_size_spec_t size_spec)

Generates an LDP instruction using pre-index encoding.

Parameters:

reg_dest1 – first destination register.
reg_dest2 – second destination register.
reg_src – source register (base address).
imm7 – 7-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::ldr(simd_fp_t reg_dest, gpr_t reg_src, uint32_t imm12, neon_size_spec_t size_spec)

Generates an LDR (12-bit immediate) instruction using unsigned offset encoding.

Parameters:

reg_dest – destination register.
reg_src – source register (base address).
imm12 – 12-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::ldrPost(simd_fp_t reg_dest, gpr_t reg_src, uint32_t imm9, neon_size_spec_t size_spec)

Generates an LDR (9-bit immediate) instruction using post-index encoding.

Parameters:

reg_dest – destination register.
reg_src – source register (base address).
imm9 – 9-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::ldrReg(simd_fp_t reg_dest, gpr_t reg_src1, gpr_t reg_src2, uint32_t option, neon_size_spec_t size_spec)

Generates an LDR (register, SIMD&FP) instruction using register offset.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register.
option – option (0:uxtw, 1:sxtw, 2:lsl, 3:sxtx).
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::mov(simd_fp_t reg_dest, gpr_t reg_src, uint32_t index, neon_size_spec_t size_spec)

Generates an MOV instruction from a general-purpose register to a vector element. This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Parameters:

reg_dest – destination SIMD&FP register.
reg_src – source general-purpose register.
index – index of the simd vector element to be replaced.
size_spec – size specifier for the SIMD&FP register.

constexpr uint32_t mini_jit::instructions::simd_fp::scvtfVec(simd_fp_t reg_dest, simd_fp_t reg_src1, arr_spec_t arr_spec)

Generates an SCVTF (vector) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – source register.
arr_spec – arrangement specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::scvtfBaseScalar(simd_fp_t reg_dest, gpr_t reg_src1, neon_size_spec_t size_spec)

Generates an SCVTF (scalar, fixed point) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::scvtfScalar(simd_fp_t reg_dest, simd_fp_t reg_src1, neon_size_spec_t size_spec)

Generates an SCVTF (scalar SIMD&FP) instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::st1(simd_fp_t reg_dst, gpr_t reg_src, uint32_t index, neon_size_spec_t size)

Generates an st1 instruction (single structure) with a lane index, e.g. st1 {V0.S}[0], [X0].

!

Parameters:

reg_dst – Destination SIMD register.
reg_src – Source general-purpose register containing the address.
index – Index of the lane to store from.
size – Size of the SIMD register (s or d).

constexpr uint32_t mini_jit::instructions::simd_fp::st1(simd_fp_t reg_dst, gpr_t reg_src, uint32_t index, neon_size_spec_t size, gpr_t reg_post_index)

Generates an st1 instruction (single structure) with a lane index and a register post-index, e.g. st1 {V0.S}[0], [X0], X1.

!

Parameters:

reg_dst – Destination SIMD register.
reg_src – Source general-purpose register containing the address.
index – Index of the lane to store from.
size – Size of the SIMD register (s or d).
post_index – Post-index register to add to the address in reg_src.

constexpr uint32_t mini_jit::instructions::simd_fp::st1(simd_fp_t reg_dst, gpr_t reg_src, uint32_t index, neon_size_spec_t size, uint32_t post_index)

Generates an st1 instruction (single structure) with a lane index and a post-index immediate, e.g. st1 {V0.S}[0], [X0], #4.

!

Parameters:

reg_dst – Destination SIMD register.
reg_src – Source general-purpose register containing the address.
index – Index of the lane to store from.
size – Size of the SIMD register (s or d).
post_index – Post-index immediate to add to the address in reg_src.

constexpr uint32_t mini_jit::instructions::simd_fp::stp(simd_fp_t reg_data1, simd_fp_t reg_data2, gpr_t reg_address, int32_t imm7, neon_size_spec_t size_spec)

Generates an STP instruction using signed offset encoding.

Parameters:

reg_data1 – first register holding the data to be transferred.
reg_data2 – second register holding the data to be transferred.
reg_address – register holding the memory address.
imm7 – 7-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::stpPost(simd_fp_t reg_data1, simd_fp_t reg_data2, gpr_t reg_address, int32_t imm7, neon_size_spec_t size_spec)

Generates an STP instruction using post-index encoding.

Parameters:

reg_data1 – first register holding the data to be transferred.
reg_data2 – second register holding the data to be transferred.
reg_address – register holding the memory address.
imm7 – 7-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::stpPre(simd_fp_t reg_data1, simd_fp_t reg_data2, gpr_t reg_address, int32_t imm7, neon_size_spec_t size_spec)

Generates an STP instruction using pre-index encoding.

Parameters:

reg_data1 – first register holding the data to be transferred.
reg_data2 – second register holding the data to be transferred.
reg_address – register holding the memory address.
imm7 – 7-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::str(simd_fp_t reg_data, gpr_t reg_address, uint32_t imm12, neon_size_spec_t size_spec)

Generates an STR (12-bit immediate) instruction using unsigned offset encoding.

Parameters:

reg_data – register holding the data to be transferred.
reg_address – register holding the memory address.
imm12 – 12-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::strPost(simd_fp_t reg_data, gpr_t reg_address, uint32_t imm9, neon_size_spec_t size_spec)

Generates an STR (9-bit immediate) instruction using post-index encoding.

Parameters:

reg_data – register holding the data to be transferred.
reg_address – register holding the memory address.
imm9 – 9-bit immediate value.
size_spec – size specifier (s, d, q).

constexpr uint32_t mini_jit::instructions::simd_fp::trn1(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an TRN1 instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register (base address).
arr_spec – arrangement specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::trn2(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an TRN2 instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register (base address).
arr_spec – arrangement specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::umov(gpr_t reg_dest, simd_fp_t reg_src, uint32_t imm5, neon_size_spec_t size_spec)

Generates an UMOV instruction.

Parameters:

reg_dest – destination register.
reg_src – source register.
imm5 – index in range 0-3.
size_spec – size specifier.

Returns:

instruction.

constexpr uint32_t mini_jit::instructions::simd_fp::zero(simd_fp_t reg, arr_spec_t arr_spec)

Generates an EOR instruction that zeros out the given register. 8B zeroes out the lower half (64 bit) of the register, while 16B zeroes out the whole register (128 bit).

Parameters:

reg – register to zero out.
arr_spec – arrangement specifier (8B or 16B).

constexpr uint32_t mini_jit::instructions::simd_fp::zip1(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an ZIP1 instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register (base address).
arr_spec – arrangement specifier.

constexpr uint32_t mini_jit::instructions::simd_fp::zip2(simd_fp_t reg_dest, simd_fp_t reg_src1, simd_fp_t reg_src2, arr_spec_t arr_spec)

Generates an ZIP2 instruction.

Parameters:

reg_dest – destination register.
reg_src1 – first source register.
reg_src2 – second source register (base address).
arr_spec – arrangement specifier.